TC358860XBG HDMI转MIPI 东芝原装进口桥接芯片

Overview
TC358860XBG converts an Embedded Display Port (eDP TM ) video stream
into an MIPI? DSI stream. There are four eDP main link lanes in
TC358860XBG, they can toggle at either 1.62, 2.16, 2.7, 3.24, 4.32, or 5.4
Gbps/link to receive up to 17.28 Gbps (5.4 Gbps * 0.8 * 4) of video stream.
The 4-data lanes dual link DSI Tx can transmit up to 8 Gbps (1 Gbps * 4 *
2) of video stream.
For input video stream with bandwidth (BW) < 4 Gbps, TC358860XBG can output the video data either with a
single DSI link or performs left-right line split to output the video data stream with dual DSI links. For input video
stream with BW requirements between 4 Gbps and 8 Gbps, left-right line split and dual DSI links usage is
necessary.
TC358860XBG provides a compression engine which compress video data with 2-to-1 ratio. This enables
TC358860XBG to receive 4K @60fps video streams at eDP Rx, compress and send out to a dual DSI link 4K
panel for display. A de-compress engine is expected in the DSI panel.
Host/eDPTx controls/configures TC358860XBG chip by using its AUX channel (I 2 C over AUX). TC358860XBG
provides mail box register/command queue for host to control/configure/command DSI panels, too. After host
writes to the command queue, TC358860XBG starts DSI “command packets” to communicate with the DSI
panels.
Alternatively, an external I 2 C master can configure TC358860XBG via I 2 C bus. Command queue address can also
be access via I 2 C bus, which means Host can use I 2 C to access command queue, which in turn, controls DSI panel
parameters.
Please note that host can not use both AUX ch. and I 2 C bus for register setting simultaneously.